1. Field of the Invention
The present invention relates to a liquid discharge head and liquid discharge apparatus.
2. Description of the Related Art
Japanese Patent Laid-Open No. 2000-141660 discloses a printhead which receives a control signal and print data via a plurality of electric contacts. This printhead includes the first contact which receives a voltage for driving a printing element, a control circuit for controlling driving of the printing element, and the second contract which receives a voltage for driving the control circuit. This printhead also includes a monitoring circuit (VDD monitoring circuit) which monitors a voltage at the second contract, and a protection circuit which stops driving of the printing element by the control circuit when the monitoring circuit detects that the voltage at the second contact has dropped. The monitoring circuit (VDD monitoring circuit) includes a first-stage inverter having an input terminal connected to the second contact (pad) connected to the VDD power supply, a plurality of inverters which are connected to the subsequent stage of the first-stage inverter, and a pull-down resistor which is connected between the second contact and ground. These inverters receive a power supply voltage VH (VH>VDD) equal to the heater driving voltage. When supply of VDD power from a printing apparatus equipped with a printhead to the printhead is cut off due to some cause, the monitoring circuit detects a voltage drop at the second contact that is caused by the cutoff, and the protection circuit operates.
Japanese Patent Laid-Open No. 2000-141660 does not describe the detailed arrangement of the inverters in the monitoring circuit. If the inverter is formed from a general CMOS (PMOS and NMOS transistors), the VDD power voltage is 3 V, and the heater driving voltage VH is 24 V, a voltage of about 21 V is applied between the gate and source of the PMOS transistor. In this state, the output logic of the first-stage inverter becomes indefinite or a large flow through current flows. To solve this problem, a PMOS transistor with a very high threshold voltage is prepared, or the gate length of the PMOS transistor is greatly increased. However, these measures newly arouse other concerns. That is, preparing a PMOS transistor with a very high threshold voltage needs to use a special semiconductor manufacturing process different from the manufacturing process of a general PMOS transistor, raising the cost. Also, a very large gate length of the PMOS transistor results in a large chip size.